The present invention relates to a liquid crystal driver which has an internal memory and a liquid crystal display which uses such a driver.
In a liquid crystal display connected to a computer, there is performed an operation in which an image is always displayed on a display screen. The image display operation is performed in such a manner that a liquid crystal driver on the liquid crystal display side successively reads display data from a display memory (or makes a display access) and supplies the read data to a liquid crystal panel at a predetermined period. In the case where there is a command from a computer side for rewriting or change and addition of display data (hereinafter referred to as updating), it is necessary to update data of the display memory (or make an updating access). Since the display data updating operation (or updating access) is not synchronous with the display operation on the liquid crystal display side and is not periodical, there may be the case where an access to the display memory for the display operation and an access to the display memory for the updating of data conflict with each other. In general, the display operation cannot be interrupted and has a preference to the updating operation. Therefore, it is necessary to change the contents of the display memory so that the updating operation does not obstruct the display operation.
The conventional liquid crystal display is constructed using, for example, a liquid crystal driver HD66107T disclosed in Hitachi LCD Controller/Driver LSI Data Book, pp. 787-806, published by Hitachi, Ltd. Such a conventional liquid crystal driver will be explained by use of FIGS. 2 to 5.
In FIG. 2, reference numeral 201 denotes a control signal bus for transferring a control signal, and numeral 202 denotes a data bus for transferring display data. Numerals 203-1 and 203-2 denote liquid crystal drivers. In the shown example, two liquid crystal drivers are used in conformity with the width of a liquid crystal panel 219 in an X (or horizontal) direction. The liquid crystal drivers 203-1 and 203-2 will hereinafter be represented generically as "liquid crystal driver 203". (Similar representation will be used for other reference numerals.) Numeral 204 denotes a timing control circuit for controlling the operation of the liquid crystal driver 203, and numeral 205 denotes a shift register for generating a signal which latches display data transferred by the data bus 202. Numeral 206 denotes a signal line for transferring latch clocks outputted from the shift register 205, numeral 207 a latch for successively taking in display data, numeral 208 a data bus for transferring data outputted from the latch 207, numeral 209 a latch for simultaneously taking in data transferred by the data bus 208, and numeral 210 a data bus for transferring data outputted from the latch 209. Numeral 211 denotes a level shifter for shifting display data transferred by the data bus 210 into a voltage level corresponding to a liquid crystal applied voltage (or a voltage to be applied to the liquid crystal of a liquid crystal panel). Numeral 212 denotes a data bus for transferring the level-shifted data, and numeral 213 denotes a voltage selector. Numeral 214 denotes an output voltage line for transferring a liquid crystal applied voltage which is selected by the voltage selector 213 in accordance with display data transferred through the data bus 212. Numeral 215 denotes a CL2 clock signal for controlling the shift register 205, and numeral 216 denotes a CL1 clock signal for taking data into the latch 209. Numeral 217 denotes a scanning circuit for selecting a line on which display is to be made. Numeral 218 denotes a scanning signal line for transferring a scanning signal generated by the scanning circuit 217, and numeral 219 denotes the display panel. Numeral 220 denotes a power supply circuit, and numerals 221 and 222 denote driving voltage lines for transferring driving voltages which drive the scanning circuit 217 and the liquid crystal driver 203, respectively.
FIG. 3 shows a block diagram of an example of a personal computer system using the liquid crystal display shown in FIG. 2. In the shown example, a display memory 307 is arranged at the exterior of the liquid crystal driver 203.
In FIG. 3, reference numeral 301 denotes a CPU, numeral 302 a main memory, numeral 303 an address bus for transferring an address, numeral 304 a data bus for transferring data, and numeral 305 a control signal bus for transferring a control signal. Numeral 306 denotes a display controller, and numeral 307 denotes the display memory for storing display data therein. Numeral 308 denotes a timing control circuit, and numeral 309 denotes a timing signal which includes a signal for accessing the display memory 307 and a signal for operating the liquid crystal driver 208. Numeral 310 denotes a selection signal for making a change-over between a display address (or address for display) and an updating address (or address for updating). Numeral 311 denotes a controller for generating a timing signal to be transferred to a signal bus 312 and an address to be transferred to a display address bus 313. Numeral 314 denotes a selector for selecting a display address and an updating address, numeral 315 an address bus for transferring an address selected by the selector 314 for accessing the display memory 307, and numeral 316 a data buffer. Numeral 317 denotes a data bus for transferring data for accessing the display memory 307, and numeral 318 denotes a data bus for transferring display data for the liquid crystal display.
FIG. 4 is a timing chart showing an access to the display memory 307 in the system shown in FIG. 3.
FIG. 5 is a timing chart showing the operation of the liquid crystal driver 203.
The liquid crystal display using the conventional liquid crystal driver will be explained using FIG. 2 again.
A control signal transferred through the signal bus 201 is inputted to the timing control circuit 204. A generated CL2 clock signal 215 is transferred to the shift register 205 which in turn generates a latch clock. The generated latch clock signal is outputted to the signal line 206. On the other hand, display data transferred through the data bus 202 to the driver 203 is successively latched by the latch 207 in accordance with the latch clock signal transferred through the signal line 206. The display data latched by the latch 207 is simultaneously stored into the latch 209 through the data bus 208 in accordance with a CL1 clock signal 216. This operation is shown in FIG. 5. Also, display data outputted from the latch 209 by the CL1 clock signal is inputted through the data bus 210 to the level shifter 211 for conversion thereof into a voltage level corresponding to a liquid crystal applied voltage. The level-shifted display data is transferred through the data bus 212 to the voltage selector 213 which in turn selects a liquid crystal applied voltage. The selected liquid crystal applied voltage is supplied through the output voltage line 214 to the liquid crystal panel 219.
Thus, the conventional liquid crystal driver has only a function of latching display data and outputting it after conversion into a liquid crystal applied voltage. This point will be explained in detail by use of FIG. 3 in conjunction with the system using the liquid crystal display driven by the conventional liquid crystal driver 203.
In the conventional system, it is necessary to transfer display data to the liquid crystal display at a fixed period. Therefore, the system requires the display memory 307 for storing display data for one screen, means for reading display data from the display memory 307 to output the read display data to the liquid crystal display, and means for updating display data to be stored in the display memory 307. Since only one system is provided for the address bus 317, the data bus 317 and the control signal 309 for the display memory 307, it is necessary that a display access for reading display data to output the read display data to the liquid crystal display and an updating access for updating display data should be made to the display memory 307 in a time division or multiplexing manner, as shown in FIG. 4. Therefore, the conventional system is constructed as follows.
The address bus 315 is constructed such that a display address or updating address is transferred to the address bus 315 in such a manner that the address bus 313 for transferring an address for the display access and the address bus 303 for transferring an address for the updating access are changed over by the selector 314. The change-over control is performed by the timing control circuit 308. The timing control circuit 308 is inputted with a control signal from the CPU 301 through the control signal bus 305 and a control signal from the controller 311 through the control signal bus 312. The two control signals perform an arbitration control which determines whether the display access or the updating access is to be made to the display memory 307. The similar holds for the data bus. Namely, in the case of the display access, the data bus 317 is constructed such that data on the data bus 317 is transferred to the data bus 318 through the buffer 316. In the case of the updating access, data on the data bus 304 is transferred to the data bus 317 through the buffer 316.
A liquid crystal driver HD66108 with internal display memory, in which a display memory is incorporated in the liquid crystal driver, has been disclosed in Hitachi LCD Controller/Driver LSI Data Book, pp. 638-690, published by hitachi, Ltd. A liquid crystal display system using such a liquid crystal driver with internal memory will now be explained by use of a block diagram shown in FIG. 6.
In FIG. 6, reference numeral 601 denotes a liquid crystal driver, numeral 602 a data bus, and numeral 603 a control signal. Numeral 604 denotes an address register, numeral 605 an X coordinate value register, numeral 606 a Y coordinate value register, numeral 607 a data bus for outputting an X coordinate value, and numeral 608 a data bus for outputting a Y coordinate value. Numeral 609 denotes an X coordinate value decoder, numeral 610 a Y coordinate value decoder, and numeral 611 an X coordinate value decode signal. Numeral 612 denotes an I/O port for controlling the input/output of display data, numeral 613 a data bus for transferring display data, and numeral 614 a Y coordinate value decode signal. Numeral 615 denotes a memory cell (which may be a static RAM), and numeral 616 denotes a data bus for transferring data for display. Numeral 617 denotes a latch, numeral 618 a data bus for transferring display data outputted from the latch 617, numeral 619 a level shifter, numeral 620 a data bus for transferring the level-shifted data, numeral 621 a voltage selector, and numeral 622 an output voltage line for transferring a liquid crystal applied voltage. Numeral 623 denotes a timing control circuit.
Next, explanation will be made of the operation of the liquid crystal driver 601.
Since the liquid crystal driver 601 uses access based on an I/O interface, the address of a register to be accessed is set into the address register 604 through the data bus 602 and the register of the address set in the address register 604 is accessed through the data bus 602. Accordingly, the updating access to the display memory is as follows. First, the address of the X coordinate value register 605 is set into the address register 604. Next, X coordinate value data to be subjected to updating is set into the X coordinate value register 605 through the data bus 602 in accordance with the address set in the address register 604. Next, the address of the Y coordinate value register 606 is set into the address register 604 and Y coordinate value data to be subjected to updating is set into the Y coordinate value register 606 through the data bus 602 in accordance with the address set in the address register 604. Next, the I/O port 612 is accessed, thereby making it possible to update data at any position in the memory cell 615. Data in the memory cell 615 for data lines of each liquid crystal driver 601 is read by the timing control circuit 623 and is stored into the latch 617. Thereafter, a voltage conversion is made by the level shifter 619 and a liquid crystal applied voltage is selected by the voltage selector 621 which in turn outputs the selected liquid crystal applied voltage. This control for reading of data from the memory cell 615 is made for every one horizontal period, thereby enabling the display on the liquid crystal display 219.
Thus, it becomes possible to update data of the memory cell 615 at any position by setting data of each register of the liquid crystal driver 601.
In the prior art shown in FIG. 3, the liquid crystal driver always takes in serialized display data, converts the data into a liquid crystal applied voltage after taking-in of display data for one horizontal line, and outputs the liquid crystal applied voltage to effect the display. Therefore, means for transferring the serialized display data to the liquid crystal driver is needed. In the prior art shown in FIG. 3, display data for one frame is stored in the display memory. Provided that the operating conditions of the liquid crystal panel are such that the frame frequency is 70 Hz, the resolving power of the liquid crystal panel is 240 in the number of vertical lines and 320 in the number of horizontal dots and the data bus width of the liquid crystal driver and the display memory is a 8-bit bus, it is necessary to always read 8-bit data from the display memory at a period of about 0.7 MHz (=70 (Hz).times.240 (lines).times.320 (dots)+8 (bits)). Accordingly, the display controller, the display memory and the liquid crystal driver must operate at the period of about 0.7 MHz and this operation muse be repeated for each frame even if a displayed image is a still picture.
The power consumption of the liquid crystal display and system increases in proportion to the operating frequency. Therefore, in order to attain a reduction in power consumption, it is necessary to reduce the operating frequency without deteriorating the operating efficiency of the system.
In the prior art shown in FIG. 3, the display access and the updating access are made to the display memory in a multiplexing manner. Since the display access has a preference to the updating access, it is necessary to perform the updating access in the intervals of the display access. Therefore, even in the case where it is desired to perform an updating processing at a high speed, the display access imposes a restriction on a processing speed for the updating access.
In the prior art shown in FIG. 6, when the display access is made to the display memory, a "BUSY" is given to the CPU to take a wait. In actual, the address register 604 has a "BUSY" bit and the CPU reads the "BUSY" bit (or makes a busy check) to make arbitration between the display access and the updating access. Thereby, in the case where the display and updating accesses to the display memory conflict with each other, the speed of the updating access becomes low. Also, when display data at any position is to be updated, the updating of display data becomes possible after the register data setting has been made four times, as mentioned above. Therefore, a considerable time is required for the updating access, thereby deteriorating the operating efficiency of the system.
In the prior art shown in FIG. 3, no consideration is taken to grayscale display and the case where the liquid crystal driver is provided in a Y-axis direction of the liquid crystal panel.